However, these loopback tests do not provide sufficient visibility into the DUT that would aid in diagnosis, making them ineffective, particularly at speeds as high as 112 Gbps. AC-coupled external loopback test with bias tees for DC test. And the addition of bias tees loopback circuits would support DC and continuity (Figure 1).įigure 1. Long circuit-board trace lengths could help make AC-coupled test more realistic, while connecting the Tx of one signal pair bank to the Rx of another would mitigate the problems of a shared PLL/DLL.

There are some workarounds that can be used on an AC-coupled external loopback. Similarly, when connecting channel pairs for loopback tests, the Tx/Rx pairs share the same PLL/DLL, again making the test too easy. AC-coupled loopback is easy to lay out on a DUT board, but the signal level the Rx receives is too low loss / too hot, making the test too easy. The simplest form is internal loopback in which the device talks to itself and never exercises the transceiver circuitry it can test internal logic only.Īnother method is AC-coupled external loopback which does exercise the I/O circuitry, but like internal loopback, it does not perform Tx/Rx eye tests, and it does not test pre-emphasis and equalization. Traditionally, HSIO loopback has been the preferred approach to HSIO test, with a simple wire or capacitor connecting a DUT’s Tx to Rx inputs. Yet another requirement is DC access for continuity and scan test. In addition, the test must verify bit error rate and confirm that a receiver can receive an off-frequency or out-of-phase signal. HSIO test involves measurement of Tx eye height and width, confirmation that a receiver can detect a low-level signal, and confirmation that continuous time linear equalization (CTLE) is effectively compensating for insertion loss. Consequently, test requirements for high-speed I/O (HSIO) test are becoming daunting. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are shrinking. HSIO Loopback Turns Challenges into Opportunities for Test at 112 Gbpsīy Dave Armstrong, Principal Test Strategist, Advantest, and Don Thompson, Senior Director of Engineering, R&D Altanovaįor both PCIe and Ethernet (IEEE 802.3) signals are getting mighty small.

Loopback tester